Designing with Xilinx(r) FPGAs: Using Vivado (Hardcover)

Designing with Xilinx(r) FPGAs: Using Vivado By Sanjay Churiwala (Editor) Cover Image

Designing with Xilinx(r) FPGAs: Using Vivado (Hardcover)

By Sanjay Churiwala (Editor)


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Chapter 1: State of the Art Programmable Logic 1
Chapter 2: Vivado Design Tools 17Chapter 3: IP Flows 23Chapter 4: Gigabit Transceivers 35Chapter 5: Memory Controllers 49Chapter 6: Processor Options 65Chapter 7: Vivado IP Integrator 75Chapter 8: SysGen for DSP 85Chapter 9: Synthesis 97Chapter 10: C Based Design 111Chapter 11: Simulation 127Chapter 12: Clocking 141Chapter 13: Stacked Silicon Interconnect (SSI) 155Chapter 14: Timing Closure 167Chapter 15: Power Analysis and Optimization 179Chapter 16: System Monitor 191Chapter 17: Hardware Debug 205Chapter 18: Emulation Using FPGAs 221Chapter 19: Partial Reconfiguration & Hierarchical Design 239.
Sanjay Churiwala is Senior Director of Engineering for Xilinx India Technology Services. He has extensive experience in the field of EDA and semiconductors R&D, as well as customer-interaction. He specializes in Clock Domain Crossings and Synchronization, STA, Power, Synthesis, Simulation, Rule based static checkers, Cell Characterization and Modeling.
Product Details ISBN: 9783319424378
ISBN-10: 3319424378
Publisher: Springer
Publication Date: November 3rd, 2016
Pages: 260
Language: English